This invention relates to digital data communication, and more particularly to circuitry and methods for producing control inputs to adjust the amount of gain provided by equalization circuitry.
The equalization circuitry may be a component of a receiver configured to receive data signals transmitted by a driver over a transmission medium (e.g., a backplane). The equalization circuitry may provide gain to data signals to compensate for attenuation caused by the transmission medium.
The equalization circuitry may include equalization stages that are controlled by control inputs to determine the amount of gain provided to the data signal. Equalization circuitry and stages are discussed in greater detail in Maangat et al. U.S. patent application Ser. No. 11/182,658, filed Jul. 14, 2005, now U.S. Patent Publication No. 2007/0014344, which is hereby incorporated by reference herein in its entirety.
Traditionally, the control inputs for the equalization stages have been generated using analog circuitry, such as, comparators, charge pumps and capacitors. In particular, a comparator may determine whether the equalization stages are providing too much or too little gain by outputting a pulse. In response to receiving the pulse from the comparator, a charge pump may increase or decrease the voltage on a capacitor to adjust the control input for the equalization stages.
However, this approach has several downsides. One downside is that the charge pump has to provide charging/discharging current to maintain the voltage level on the capacitor. Therefore, it would be difficult to adjust the amount of gain in the equalization circuitry in precise increments because the charging/discharging action of the charge pump depends on the current values and the duration of the enable time pulses from the comparator, which are both difficult to control. Another downside is that current leakage from the capacitor increases jitter and the control input cannot be locked after the appropriate control input for the equalization circuitry has been determined. Hysteresis cannot be added to help reduce jitter in this analog approach because at optimum equalization, the capacitor charges 50% of the time and discharges 50% of the time.